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w9812g2gh 1m x 4 banks x 32bits sdram publication release date:may 19, 2008 - 1 - revision a09 table of contents- 1. general description ......................................................................................................... 3 2. features ................................................................................................................................. 3 3. available part number ...................................................................................................... 3 4. pin configuration ............................................................................................................... 4 5. pin description ..................................................................................................................... 5 6. block diagram ...................................................................................................................... 6 7. functional description .................................................................................................... 7 7.1 power up and initialization ............................................................................................ 7 7.2 programming mode register ......................................................................................... 7 7.3 bank activate command ................................................................................................ 7 7.4 read and write access modes ...................................................................................... 7 7.5 burst read command .................................................................................................... 8 7.6 burst write command .................................................................................................... 8 7.7 read interrupted by a read ........................................................................................... 8 7.8 read interrupted by a write ........................................................................................... 8 7.9 write interrupted by a write ........................................................................................... 8 7.10 write interrupted by a read ........................................................................................... 8 7.11 burst stop command ..................................................................................................... 9 7.12 addressing sequence of sequential mode .................................................................... 9 7.13 addressing sequence of interleave mode ..................................................................... 9 7.14 auto-precharge command ........................................................................................... 10 7.15 precharge command ................................................................................................... 10 7.16 self refresh command ................................................................................................ 10 7.17 power down mode ....................................................................................................... 11 7.18 no operation command .............................................................................................. 11 7.19 deselect command ...................................................................................................... 11 7.20 clock suspend mode ................................................................................................... 11 8. operation mode ................................................................................................................. 12 8.1 simplified stated diagram ........................................................................................... 13 9. electrical characteristics ......................................................................................... 14 9.1 absolute maximum ratings ......................................................................................... 14 9.2 recommended dc operating conditions .................................................................... 14
w9812g2gh publication release date:may 19, 2008 - 2 - revision a09 9.3 capacitance ................................................................................................................. 15 9.4 dc characteristics ....................................................................................................... 15 9.5 ac characteristics and operating condition ............................................................... 16 10. timing waveforms ............................................................................................................. 19 10.1 command input timing ................................................................................................ 19 10.2 read timing ................................................................................................................. 20 10.3 control timing of input/output data ............................................................................ 21 10.4 mode register set cycle ............................................................................................. 22 11. operating timing example ............................................................................................. 23 11.1 interleaved bank read (burst length = 4, cas latency = 3) ..................................... 23 11.2 interleaved bank read (burst length = 4, cas latency = 3, auto-precharge) .......... 24 11.3 interleaved bank read (burst length = 8, cas latency = 3) ..................................... 25 11.4 interleaved bank read (burst length = 8, cas latency = 3, auto-precharge) .......... 26 11.5 interleaved bank write (burst length = 8) ................................................................... 27 11.6 interleaved bank write (burst length = 8, auto-precharge) ........................................ 28 11.7 page mode read (burst length = 4, cas latency = 3) .............................................. 29 11.8 page mode read / write (burst length = 8, cas latency = 3) .................................. 30 11.9 auto-precharge read (burst length = 4, cas latency = 3) ....................................... 31 11.10 auto-precharge write (burst length = 4) ..................................................................... 32 11.11 auto refresh cycle ...................................................................................................... 33 11.12 self refresh cycle ....................................................................................................... 34 11.13 burst read and single write (burst length = 4, cas latency = 3) ............................ 35 11.14 power down mode ....................................................................................................... 36 11.15 auto-precharge timing (read cycle) .......................................................................... 37 11.16 auto-precharge timing (write cycle) ........................................................................... 38 11.17 timing chart of read to write cycle ........................................................................... 39 11.18 timing chart of write to read cycle ........................................................................... 39 11.19 timing chart of burst stop cycle (burst stop command) ........................................... 40 11.20 timing chart of burst stop cycle (precharge command) ........................................... 40 11.21 cke/dqm input timing (write cycle) .......................................................................... 41 11.22 cke/dqm input timing (read cycle) ......................................................................... 42 12. package specification .................................................................................................... 43 12.1 86l tsop (ii)-400 mil .................................................................................................. 43 13. revision history ................................................................................................................ 44
w9812g2gh publication release date:may 19, 2008 - 3 - revision a09 1. general description w9812g2gh is a high-speed synchronous dynamic random access memory (sdram), organized as 1,048,576 words 4 banks 32 bits. using pipelined architecture and 0.11 m process technology, w9812g2gh delivers a data bandwidth of up to 200m words per second (-5). for different application, w9812g2gh is sorted into the following speed grades: -5/-6/-6c/-6i and -75. the ?5 is compliant to the 200mhz/cl3 specification. the ?6/-6c/-6i is compliant to the 166mhz/cl3 specification. (the grade of and -6c/-6i is t ih =0.8ns and the -6i grade which is guaranteed to support -40c ~ 85c.). the -75 is compliant to the 133mhz/cl3 specification. accesses to the sdram are burst oriented. c onsecutive memory location in one page can be accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an active command. column addresses are automatically gener ated by the sdram internal counter in burst operation. random column read is also possible by providing its address at each clock cycle. the multiple bank nature enables interleaving amon g internal banks to hide the precharging time. by having a programmable mode register, the syst em can change burst length, latency cycle, interleave or sequential burst to maximize its performance. w9812g2gh is ideal for main memory in high performance applications. 2. features ? 3.3v 0.3 v for -5/-6/-6i/-75 grade power supply 2.7v 3.6v for -6c grade power supply 2.3v 2.7v, @ t ck >10ns for -6c grade power supply ? up to 200 mhz clock frequency ? 1,048,576 words 4 banks 32 bits organization ? self refresh mode ? cas latency: 2 and 3 ? burst length: 1, 2, 4, 8 and full page ? burst read, single writes mode ? byte data controlled by dqm0-3 ? auto-precharge and controlled precharge ? 4k refresh cycles/64 ms ? interface: lvttl ? packaged in tsop ii 86-pin , using lead free materials with rohs compliant 3. available part number part number speed maximum self refresh current operating temperature w9812g2gh-5 200mhz/cl3 2ma 0 c ~ 70 c w9812g2gh-6 166mhz/cl3 2ma 0 c ~ 70 c w9812g2gh-6c 166mhz/cl3 2ma 0 c ~ 70 c W9812G2GH-6I 166mhz/cl3 2ma -40 c ~ 85 c w9812g2gh-75 133mhz/cl3 2ma 0 c ~ 70 c
w9812g2gh publication release date:may 19, 2008 - 4 - revision a09 4. pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 78 79 80 81 82 83 84 85 86 vdd dq0 vddq dq1 dq2 vssq dq3 dq4 vddq dq5 dq6 vssq dq7 nc vdd dqm0 we# cas# ras# cs# a11 bs0 bs1 a10 a0 a1 a2 dqm2 vdd nc dq16 vssq dq17 dq18 vddq dq19 dq20 vssq dq21 dq22 vddq dq23 vdd vss dq15 vssq dq14 dq13 vddq dq12 dq11 vssq dq10 dq9 vddq dq8 nc vss dqm1 nc nc clk cke a9 a8 a7 a6 a5 a4 a3 dqm3 vss nc dq31 vddq dq30 dq29 vssq dq28 dq27 vddq dq26 dq25 vssq dq24 vss
w9812g2gh publication release date:may 19, 2008 - 5 - revision a09 5. pin description pin number pin name function description 25-27, 60-66, 24,21 a0 ? a11 address multiplexed pins for row and column address. row address: a0 ? a11. column address: a0 ? a7. a10 is sampled during a precharge command to determine if all banks are to be precharged or bank selected by bs0, bs1. 22,23 bs0, bs1 bank select select bank to activate during row address latch time, or bank to read/write during address latch time. 2,4,5,7,8, 10,11,13,74, 76,77,79,80,82,83,85, 31,33,34,36,37,39,40, 42,45,47,48,50,51,53, 54,56 dq0 ? dq31 data input/ output multiplexed pins for data output and input. 20 cs chip select disable or enable the command decoder. when command decoder is disabled, new command is ignored and previous operation continues. 19 ras row address strobe command input. when sampled at the rising edge of the clock, ras , cas and we define the operation to be executed. 18 cas column address strobe referred to ras 17 we write enable referred to ras 16,71,28,59 dqm0~3 input/output mask the output buffer is placed at hi-z (with latency of 2) when dqm is sampled high in read cycle. in write cycle, sampling dqm high will block the write operation with zero latency. 68 clk clock inputs system clock used to sample inputs on the rising edge of clock. 67 cke clock enable cke controls the clock activation and deactivation. when cke is low, power down mode, suspend mode, or self refresh mode is entered. 1,15,29,43 vdd power (+3.3v) power for input buffers and logic circuit inside dram. 44,58,72,86 vss ground ground for input buffers and logic circuit inside dram. 3,9,35,41,49,55 ,75,81 vddq power (+3.3v) for i/o buffer separated power from vdd, to improve dq noise immunity. 6,12,32,38,46,52,78, 84 vssq ground for i/o buffer separated ground from vss, to improve dq noise immunity. 14,30,57,69,70,73 nc no connection no connection
w9812g2gh publication release date:may 19, 2008 - 6 - revision a09 6. block diagram dq0 dq31 dqmn clk cke cs ras cas we a10 a0 a9 a11 bs0 bs1 . clock buffer command decoder address buffer refresh counter column counter control signal generator mode register and emrs column decoder sense amplifier cell array bank #2 column decoder sense amplifier cell array bank #0 column decoder sense amplifier cell array bank #3 data control circuit dq buffer column decoder sense amplifier cell array bank #1 note: the cell array configuration is 4096 * 256 * 32 dmn row decoder row decoder row decoder row decoder
w9812g2gh publication release date:may 19, 2008 - 7 - revision a09 7. functional description 7.1 power up and initialization the default power up state of the mode register is unspecified. the following power up and initialization sequence need to be followed to guar antee the device being preconditioned to each user specific needs. during power up, all vdd and vddq pins must be ramp up simultaneously to the specified voltage when the input signals are held in the ?nop? stat e. the power up voltage must not exceed vdd +0.3v on any of the input pins or vdd supplies. afte r power up, an initial pause of 200 s is required followed by a precharge of all banks using the prec harge command. to prevent data contention on the dq bus during power up, it is required that the dqm and cke pins be held high during the initial pause period. once all banks have been precharged, the mode register set command must be issued to initialize the mode register. an additional eight auto refresh cycles (cbr) are also required before or after programming the mode register to ensure proper subsequent operation. 7.2 programming mode register after initial power up, the mode register set command must be issued for proper device operation. all banks must be in a precharged state and cke mu st be high at least one cycle before the mode register set command can be issued. the mode register set command is activated by the low signals of ras , cas , cs and we at the positive edge of the clock. the address input data during this cycle defines the parameters to be set as shown in the mode register operation table. a new command may be issued following the mode register set command once a delay equal to t rsc has elapsed. please refer to the next page for mo de register set cycle and operation table. 7.3 bank activate command the bank activate command must be applied before any read or write operation can be executed. the operation is similar to ras activate in edo dram. the delay from when the bank activate command is applied to when the first read or write operation can begin must not be less than the ras to cas delay time (t rcd ). once a bank has been activated it must be precharged before another bank activate command can be issued to the same bank. the minimum time interval between successive bank activate commands to the same bank is determined by the ras cycle time of the device (t rc ). the minimum time interval between interleaved bank activate commands (bank a to bank b and vice versa) is the bank to bank delay time (t rrd ). the maximum time that each bank can be held active is specified as t ras (max). 7.4 read and write access modes after a bank has been activated, a read or write cy cle can be followed. this is accomplished by setting ras high and cas low at the clock rising edge after minimum of t rcd delay. we pin voltage level defines whether the access cycle is a read operation ( we high), or a write operation ( we low). the address inputs determine the starting column address. reading or writing to a different row within an ac tivated bank requires the bank be precharged and a new bank activate command be issued. when more than one bank is activated, interleaved bank read or write operations are possible. by using the programmed burst length and alternating the access and precharge operations between multiple banks, seamless data access operation among
w9812g2gh publication release date:may 19, 2008 - 8 - revision a09 many different pages can be realized. read or write commands can also be issued to the same bank or between active banks on every clock cycle. 7.5 burst read command the burst read command is initiated by applying logic low level to cs and cas while holding ras and we high at the rising edge of the clock. the add ress inputs determine the starting column address for the burst. the mode register sets type of burst (sequential or interleave) and the burst length (1, 2, 4, 8, full page) during the mode r egister set up cycle. table 2 and 3 in the next page explain the address sequence of interleave mode and sequential mode. 7.6 burst write command the burst write command is initiated by applying logic low level to cs , cas and we while holding ras high at the rising edge of the clock. the address inputs determine the starting column address. data for the first burst write cycle must be applied on the dq pins on the same clock cycle that the write command is issued. the remaini ng data inputs must be supplied on each subsequent rising clock edge until the burst length is completed. data supplied to the dq pins after burst finishes will be ignored. 7.7 read interrupted by a read a burst read may be interrupted by another read co mmand. when the previous burst is interrupted, the remaining addresses are overrid den by the new read address with the full burst length. the data from the first read command continues to appea r on the outputs until the cas latency from the interrupting read command the is satisfied. 7.8 read interrupted by a write to interrupt a burst read with a write comm and, dqm may be needed to place the dqs (output drivers) in a high impedance state to avoid data contention on the dq bus. if a read command will issue data on the first and second clocks cycles of the write operation, dqm is needed to insure the dqs are tri-stated. after that point the write command will have control of the dq bus and dqm masking is no longer needed. 7.9 write interrupted by a write a burst write may be interrupted before completion of the burst by another write command. when the previous burst is interrupted, the remaining addr esses are overridden by the new address and data will be written into the device until the programmed burst length is satisfied. 7.10 write interrupted by a read a read command will interrupt a burst write operat ion on the same clock cycle that the read command is activated. the dqs must be in the high impedance state at l east one cycle before the new read data appears on the outputs to avoi d data contention. when the read command is activated, any residual data from t he burst write cycl e will be ignored.
w9812g2gh publication release date:may 19, 2008 - 9 - revision a09 7.11 burst stop command a burst stop command may be used to terminate the existing burst operation but leave the bank open for future read or write commands to the same page of the active bank, if t he burst length is full page. use of the burst stop command during other bur st length operations is illegal. the burst stop command is defined by having ras and cas high with cs and we low at the rising edge of the clock. the data dqs go to a high impedance stat e after a delay which is equal to the cas latency in a burst read cycle interrupted by burst stop. if a burst stop command is issued during a full page burst write operation, then any residual data from the burst write cycle will be ignored. 7.12 addressing sequence of sequential mode a column access is performed by increasing the addr ess from the column address which is input to the device. the disturb address is varied by the burst length as shown in table 2. table 2 address sequence of sequential mode data access address burst length data 0 n bl = 2 (disturb address is a0) data 1 n + 1 no address carry from a0 to a1 data 2 n + 2 bl = 4 (disturb addresses are a0 and a1) data 3 n + 3 no address carry from a1 to a2 data 4 n + 4 data 5 n + 5 bl = 8 (disturb addresses are a0, a1 and a2) data 6 n + 6 no address carry from a2 to a3 data 7 n + 7 7.13 addressing sequence of interleave mode a column access is started in the input column add ress and is performed by inverting the address bit in the sequence shown in table 3. table 3 address sequence of interleave mode data access address burst length data 0 a8 a7 a6 a5 a4 a3 a2 a1 a0 bl = 2 data 1 a8 a7 a6 a5 a4 a3 a2 a1 a 0 data 2 a8 a7 a6 a5 a4 a3 a2 a 1 a0 bl = 4 data 3 a8 a7 a6 a5 a4 a3 a2 a 1 a 0 data 4 a8 a7 a6 a5 a4 a3 a 2 a1 a0 bl = 8 data 5 a8 a7 a6 a5 a4 a3 a 2 a1 a 0 data 6 a8 a7 a6 a5 a4 a3 a 2 a 1 a0 data 7 a8 a7 a6 a5 a4 a3 a 2 a 1 a 0
w9812g2gh publication release date:may 19, 2008 - 10 - revision a09 7.14 auto-precharge command if a10 is set to high when the read or write command is issued, then the auto-precharge function is entered. during auto-precharge, a read command will execute as normal with the exception that the active bank will begin to precharge automatically before all burst read cycles have been completed. regardless of burst length, it will begin a certain nu mber of clocks prior to the end of the scheduled burst cycle. the number of clocks is determined by cas latency. a read or write command with auto-precharge can not be interrupted before the entire burst operation is completed. therefore, use of a read, write or precharge command is prohibited during a read or write cycle with auto-precharge. once t he precharge operation has started, the bank cannot be reactivated until the precharge time (t rp ) has been satisfied. issue of auto-precharge command is illegal if the burst is set to full page length. if a 10 is high when a write command is issued, the write with auto-precharge function is initiated. the sdram automatically enters the precharge operation two clocks delay from the last burst write cy cle. this delay is referred to as write t wr . the bank undergoing auto-precharge can not be reactivated until t wr and t rp are satisfied. this is referred to as t dal , data-in to active delay (t dal = t wr + t rp ). when using the auto-precharge command, the interval between the bank activate command and the beginni ng of the internal precharge operation must satisfy t ras (min). 7.15 precharge command the precharge command is used to precharge or close a bank that has been activated. the precharge command is entered when cs , ras and we are low and cas is high at the rising edge of the clock. the precharge command can be used to precharge each bank separately or all banks simultaneously. three address bits, a10, bs0 and bs1 are used to define which bank(s) is to be precharged when the command is issued. after the precharge command is issued, the precharged bank must be reactivated before a new read or wr ite access can be executed. the delay between the precharge command and the activate command must be greater than or equal to the precharge time (t rp ). 7.16 self refresh command the self refresh command is defined by having cs , ras , cas and cke held low with we high at the rising edge of the clock. all banks must be idle prior to issuing the self refresh command. once the command is registered, cke must be held low to keep the device in self refresh mode. when the sdram has entered self refresh mode all of the external control signals, except cke, are disabled. the clock is internally disabled during self refresh operation to save power. the device will exit self refresh operation after cke is returned high. a minimum delay time is required when the device exits self refresh operati on and before the next command can be issued. this delay is equal to the t ac cycle time plus the self refresh exit time. if, during normal operation, auto refresh cycles are issued in bursts (as opposed to being evenly distributed), a burst of 4,096 au to refresh cycles should be completed just prior to entering and just after exiting the self refresh mode. the peri od between the auto refresh command and the next command is specified by t rc .
w9812g2gh publication release date:may 19, 2008 - 11 - revision a09 7.17 power down mode the power down mode is initiated by holding cke lo w. all of the receiver circuits except cke are gated off to reduce the power. the power down mode does not perform any refresh operations, therefore the device can not remain in power down mode longer than the refresh period (t ref ) of the device. the power down mode is exited by bringing c ke high. when cke goes high, a no operation command is required on the next rising clock edge, depending on t ck . the input buffers need to be enabled with cke held high for a period equal to t cks (min) + t ck (min). 7.18 no operation command the no operation command should be used in cases w hen the sdram is in a idle or a wait state to prevent the sdram from registering any unwanted commands between operations. a no operation command is registered when cs is low with ras , cas , and we held high at the rising edge of the clock. a no operation command will not terminate a previous operation that is still executing, such as a burst read or write cycle. 7.19 deselect command the deselect command performs the same function as a no operation command. deselect command occurs when cs is brought high, the ras , cas , and we signals become don?t cares. 7.20 clock suspend mode during normal access mode, cke must be held high enabling the clock. when cke is registered low while at least one of the banks is active, clock suspend mode is entered. the clock suspend mode deactivates the internal clock and suspends any clocked operation t hat was currently being executed. there is a one clock delay between the registrati on of cke low and the time at which the sdram operation suspends. while in clock suspend mode, the sdram ignores any new commands that are issued. the clock suspend mode is exited by bri nging cke high. there is a one clock cycle delay from when cke returns high to when clock suspend mode is exited.
w9812g2gh publication release date:may 19, 2008 - 12 - revision a09 8. operation mode fully synchronous operations are performed to la tch the commands at the positive edges of clk. table 1 shows the truth table for the operation commands. table 1 truth table (note (1), (2)) command device state cken-1 cken dqm bs0, 1 a10 a0 ? a9 a11 cs ras cas we bank active idle h x x v v v l l h h bank precharge any h x x v l x l l h l precharge all any h x x x h x l l h l write active (3) h x x v l v l h l l write with auto-precharge active (3) h x x v h v l h l l read active (3) h x x v l v l h l h read with auto-precharge active (3) h x x v h v l h l h mode register set idle h x x v v v l l l l no ? operation any h x x x x x l h h h burst stop active (4) h x x x x x l h h l device deselect any h x x x x x h x x x auto - refresh idle h h x x x x l l l h self - refresh entry idle h l x x x x l l l h self refresh exit idle ( s.r. ) l l h h x x x x x x x x h l x h x h x x clock suspend mode entry active h l x x x x x x x x power down mode entry idle active (5) h h l l x x x x x x x x h l x h x h x x clock suspend mode exit acti ve l h x x x x x x x x power down mode exit any (power down) l l h h x x x x x x x x h l x h x h x x data write/output enable ac tive h x l x x x x x x x data write/output disable active h x h x x x x x x x notes: (1) v = valid x = don?t care l = low level h = high level (2) cken signal is input level when commands are provided. cken-1 signal is the input level one clock cycle before the command is issued. (3) these are state of bank designated by bs0, bs1 signals. (4) device state is full page burst operation. (5) power down mode can not be entered in the burst cycle. when this command asserts in the burst cycle, device state is clock suspend mode.
w9812g2gh publication release date:may 19, 2008 - 13 - revision a09 8.1 simplified stated diagram mode register set idle cbr refresh self refresh row active power down precharge power on active power down write write suspend writea writea suspend read suspend read reada suspend reada precharge mrs ref act cke cke cke cke cke cke cke cke cke cke s e l f s e l f e x i t c k e c k e w r i t e w i t h read write a u t o p r e c h a r g e a u t o p r e c h a r g e r e a d w i t h write w r i t e r e a d p r e ( p r e c h a r g e t e r m i n a t i o n ) p r e ( p r e c h a r g e t e r m i n a t i o n ) read b s t b s t pre manual input automatic sequence mrs = mode register set ref = refresh act = active pre = precharge writea = write with auto-precharge reada = read with auto-precharge
w9812g2gh publication release date:may 19, 2008 - 14 - revision a09 9. electrical characteristics 9.1 absolute maximum ratings parameter symbol rating unit notes input, column output voltage v in , v out -0.3~ vdd + 0.3v v 1 power supply voltage vdd , vdd q -0.3~4.6v v 1 operating temperatur e(-5/-6/-6c/-75) t opr 0 ~ 70 c 1 operating temperature (-6i) t opr -40 ~ 85 c 1 storage temperature t stg -55 ~ 150 c 1 soldering temperature (10s) t solder 260 c 1 power dissipation p d 1 w 1 short circuit output current i out 50 ma 1 note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life and reliability of the device. 9.2 recommended dc operating conditions (t a = 0 to 70 c for -5/-6/-6c/-75, t a = -40 to 85c for -6i) parameter sym. min. typ. max. unit notes power supply voltage (-5/-6/-75) vdd 3.0 3.3 3.6 v power supply voltage (for i/o buffer) (-5/-6/-75) vdd q 3.0 - 3.6 v power supply voltage (-6c) vdd 2.7 3.3 3.6 v power supply voltage (for i/o buffer) ( -6c) vdd q 2.7 - 3.6 v power supply voltage (-6c @ tck>10ns) vdd 2.3 2.5 2.7 v power supply voltage (for i/o buffer) (-6c @ tck>10ns) vdd q 2.3 - 2.7 v input high voltage v ih 2 - vdd +0.3 v 1 input low voltage v il -0.3 - +0.8 v 2 input high voltage (-6c @ vdd=2.3v~2.7v) v ih 0.8* vdd q - vdd +0.3 v 1 input low voltage (-6c @ vdd=2.3v~2.7v) v il -0.3 - 0.2* vdd q v 2 output logic high voltage v oh 2.4 - - v i oh = -2ma output logic low voltage v ol - - 0.4 v i ol = 2ma output logic high voltage (-6c @ vddq=2.3v~2.7v) v oh 2 - - v i oh = -2ma output logic low voltage (-6c @ vddq=2.3v~2.7v) v ol - - 0.4 v i ol = 2ma input leakage current i i(l) -5 - 5 a 3 output leakage current i o(l) -5 - 5 a 4
w9812g2gh publication release date:may 19, 2008 - 15 - revision a09 note: 1. v ih (max.) = v dd /v ddq +1.2v for pulse width < 5 ns. 2. v il (min.) = v ss /v ssq -1.2v for pulse width < 5 ns. 3. any input 0v < v in < v ddq. input leakage currents include hi-z output leakage for all bi-directional buffers with tri-state outputs. 4. output disabled, 0v v out v ddq 9.3 capacitance (vdd =3.3v0.3v for -5/-6/-6i/-75, vdd=2.7v-3.6v for -6c, t a = 25 c, f = 1 mhz) parameter sym. min. max. unit input capacitance (a0 to a10, bs0, bs1, cs , ras , cas , we , dqm, cke) c i 3.8 pf input capacitance (clk) c clk 3.5 pf input/output capacitance (dq0 ? dq31) c io 4 6.5 pf note: these parameters are periodically sampled and not 100% tested. 9.4 dc characteristics (vdd = 3.3v0.3v for -5/-6/-75, vdd=2.7v-3.6v for -6c, on t a = 0~70c, vdd = 3.3v0.3v for -6i on t a = -40 ~85 c) max. parameter sym. -5 -6/-6c/-6i -75 unit notes operating current t ck = min., t rc = min. active precharge command cycling without burst operation 1 bank operation i dd1 150 130 110 3 standby current t ck = min., cs = v ih v ih/l = v ih (min.)/v il (max.) cke = v ih i dd2 55 45 35 3 bank: inactive state cke = v il (power down mode) i dd2p 2 2 2 3 standby current clk = v il , cs = v ih v ih/l =v ih (min.)/v il (max.) cke = v ih i dd2s 15 15 15 bank: inactive state cke = v il (power down mode) i dd2ps 2 2 2 ma no operating current t ck = min., cs = v ih (min.) cke = v ih i dd3 75 70 65 bank: active state (4 banks) cke = v il (power down mode) i dd3p 15 15 15 burst operating current (t ck = min.) read/write command cycling i dd4 220 200 180 3, 4 auto refresh current (t ck = min.) auto refresh command cycling i dd5 250 230 210 3 self refresh current self refresh mode (cke = 0.2v) i dd6 2 2 2
w9812g2gh publication release date:may 19, 2008 - 16 - revision a09 9.5 ac characteristics and operating condition (vdd = 3.3v 0.3v, t a = 0 to 70 c for -5/-6/-75, vdd=2.7v-3.6v for -6c, t a = 0 to 70 c, vdd = 3.3v 0.3v, t a = -40 to 85c for -6i) (notes: 5, 6, 7, 8, 9, 10) -5 -6 -6c/-6i -75 parameter sym. min. max. min. max. min. max. min. max. unit n ote s ref/active to ref/active command period t rc 55 60 60 65 active to precharge command period t ras 40 100000 42 100000 42 100000 45 100000 ns active to read/write command delay time t rcd 15 18 18 20 read/write(a) to read/write(b) command period t ccd 1 1 1 1 t ck precharge to active command period t rp 15 18 18 20 active(a) to active(b) command period t rrd 10 12 12 15 ns cl* = 2 2 2 -- 2 write recovery time cl* = 3 t wr 2 2 2 2 t ck cl* = 2 10 1000 10 1000 10 1000 10 1000 cl* = 3 5 1000 6 1000 6 1000 7.5 1000 clk cycle time cl* = 3 (vdd=2.3v~2.7v) t ck -- -- -- -- 10 1000 -- -- clk high level width t ch 2 2 2 2.5 8 clk low level width t cl 2 2 2 2.5 8 cl* = 2 6 6 6 6 access time from clk cl* = 3 t ac 4.5 5 5 5.4 9 output data hold time t oh 3 3 3 3 9 cl* = 2 6 6 6 6 output data high impedance time cl* = 3 t hz 4.5 5 5 5.4 7 output data low impedance time t lz 0 0 0 0 9 power down mode entry time t sb 0 5 0 6 0 6 0 7.5 ns transition time of clk (rise and fall) t t 1 1 1 1 data-in set-up time t ds 1.5 1.5 1.5 1.5 8 data-in hold time 1.0 1.0 0.8 1.0 8 data-in hold time (vdd=2.3v~2.7v) t dh -- -- 1.0 -- address set-up time t as 1.5 1.5 1.5 1.5 8 address hold time 1.0 1.0 0.8 1.0 8 address hold time (vdd=2.3v~2.7v) t ah -- -- 1.0 -- cke set-up time t cks 1.5 1.5 1.5 1.5 8 cke hold time 1.0 1.0 0.8 1.0 8 cke hold time (vdd=2.3v~2.7v) t ckh -- -- 1.0 -- command set-up time t cms 1.5 1.5 1.5 1.5 8 command hold time 1.0 1.0 0.8 1.0 8 command hold time (vdd=2.3v~2.7v) t cmh -- -- 1.0 -- refresh time t ref 64 64 64 64 ms mode register set cycle time t rsc 10 12 12 15 ns exit self refresh to active command t xsr 70 72 72 75 ns *cl = cas latency
w9812g2gh publication release date:may 19, 2008 - 17 - revision a09 notes: 1. operation exceeds ?absolute maximum rati ngs? may cause permanent damage to the devices. 2. all voltages are referenced to vss ? 2.7v~3.6v power supply for -6c speed grades. ? 2.3v~2.7v, @ t ck >10ns power supply for -6c speed grades. 3. these parameters depend on the cycle rate and listed values are measured at a cycle rate with the minimum values of t ck and t rc . 4. these parameters depend on the output loading conditions. specified values are obtained with output open. 5. power up sequence is further described in the ?functional description? section. 6. ac testing conditions parameter conditions output reference level 1.4v output reference level (-6c, vdd/vddq=2.3v~2.7v) 1.2v output load see diagram below transition time (t t : tr/tf) of input signal 1/1 ns input reference level 1.4v input reference level (-6c, vdd/vddq=2.3v~2.7v) 1.2v 50 ohms ac test load (1) z = 50 ohms output 30pf 1.4v 50 ohms ac test load (2) z = 50 ohms output 30pf 1.2v (-6c, vdd/vddq=2.3v 2.7v)
w9812g2gh publication release date:may 19, 2008 - 18 - revision a09 7. t hz defines the time at which the outputs achieve the open circuit condition and is not referenced to output level. 8. assumed input rise and fall time (t t ) = 1ns. if tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf) /2-1]ns should be added to the parameter (the t t maximum can?t be more than 10ns for low frequency application.) 9. if clock rising time (t t ) is longer than 1ns, (t t /2-0.5)ns should be added to the parameter.
w9812g2gh publication release date:may 19, 2008 - 19 - revision a09 10. timing waveforms 10.1 command input timing clk a0-a11 bs0, 1 v ih v il t cmh t cms t ch t cl t t t t t cks t ckh t ckh t cks t cks t ckh cs ras cas we cke t cms t cmh t cms t cmh t cms t cmh t cms t cmh t as t ah t ck
w9812g2gh publication release date:may 19, 2008 - 20 - revision a09 10.2 read timing read cas latency t ac t lz t ac t oh t hz t oh burst length read command clk cs ras cas we a0-a11 bs0, 1 dq valid data-out valid data-out
w9812g2gh publication release date:may 19, 2008 - 21 - revision a09 10.3 control timing of input/output data t cmh t cms t cmh t cms t ds t dh t ds t dh t ds t dh t ds t dh valid data-out valid data-out valid data-out valid data-in valid data-in valid data-in valid data-in t ckh t cks t ckh t cks t ds t dh t ds t dh t dh t ds t ds t dh valid data-in valid data-in valid data-in valid data-in t cmh t cms t cmh t cms t oh t ac t oh t ac t oh t hz t lz t ac t oh t ac t ckh t cks t ckh t cks t oh t ac t oh t ac t oh t ac t oh t ac valid data-out valid data-out valid data-out clk dqm dq0 -31 (word mask) (clock mask) clk cke dq0 -31 clk control timing of input data control timing of output data (output enable) (clock mask) dqm dq0 -31 cke clk dq0 -31 open
w9812g2gh publication release date:may 19, 2008 - 22 - revision a09 10.4 mode register set cycle a0 a1 a2 a3 a4 a5 a6 burst length addressing mode cas latency (test mode) a8 reserved a0 a7 a0 a9 a0 write mode a10 a0 a11 bs0 "0" "0" a0 a3 a0 addressing mode a0 0 a0 sequential a0 1 a0 interleave a0 a9 single write mode a0 0 a0 burst read and burst write a0 1 a0 burst read and single write a0 a0 a2 a1 a0 a0 0 0 0 a0 0 0 1 a0 0 1 0 a0 0 1 1 a0 1 0 0 a0 1 0 1 a0 1 1 0 a0 1 1 1 a0 burst length a0 sequential a0 interleave 1 a0 1 a0 2 a0 2 a0 4 a0 4 a0 8 a0 8 a0 reserved a0 reserved a0 full page a0 cas latency a0 reserved a0 reserved 2 a0 3 reserved a0 a6 a5 a4 a0 0 0 0 a0 0 1 0 a0 0 1 1 a0 1 0 0 a0 0 0 1 t rsc t cms t cmh t cms t cmh t cms t cmh t cms t cmh t as t ah clk cs ras cas we a0-a11 bs0,1 register set data next command a0 reserved "0" "0" bs1 "0" "0"
w9812g2gh publication release date:may 19, 2008 - 23 - revision a09 11. operating timing example 11.1 interleaved bank read (burst length = 4, cas latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 clk dq cke dqm a0-a9, a11 a10 bs1 we cas ras cs bs0 t rc t rc t rc t rc t ras t rp t ras t rp t rp t ras t ras t rcd t rcd t rcd t rcd t ac t ac t ac t ac t rrd t rrd t rrd t rrd active read active read active active active read read precharge precharge precharge raa rbb rac rbd rae raa caw rbb cbx rac cay rbd cbz rae aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3 cy0 cy1 cy2 cy3 bank #0 idle bank #1 bank #2 bank #3
w9812g2gh publication release date:may 19, 2008 - 24 - revision a09 11.2 interleaved bank read (burst length = 4, cas latency = 3, auto-precharge) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 clk cke dqm a0-a9, a11 a10 bs1 we cas ras cs bs0 t rc t rc t rc t ras t rp t ras t rp t ras t rp t ras t rcd t rcd t rcd t rcd t ac t ac t ac t ac t rrd t rrd t rrd t rrd active read active read active active active read read t rc raa rbb rac rbd rae dq aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3 cy0 cy1 cy2 cy3 dz0 * ap is the internal precharge start timing bank #0 idle bank #1 bank #2 bank #3 ap* ap* ap* raa caw rbb cbx rac cay rbd rae cbz
w9812g2gh publication release date:may 19, 2008 - 25 - revision a09 11.3 interleaved bank read (bur st length = 8, cas latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 t rc t rc t rc t ras t rp t ras t rp t ras t rp t rcd t rcd t rcd t rrd t rrd raa raa cax rbb rbb cby rac rac caz ax0 ax1 ax2 ax3 ax4 ax5 ax6 by0 by1 by4 by5 by6 by7 cz0 clk dq cke dqm a0-a9, a11 a10 bs0 we cas ras cs bs1 active read precharge active read precharge active t ac t ac read precharge t ac bank #0 idle bank #1 bank #2 bank #3
w9812g2gh publication release date:may 19, 2008 - 26 - revision a09 11.4 interleaved bank read (burst length = 8, cas latency = 3, auto-precharge) a0-a9, a11 bank #0 idle bank #1 bank #2 bank #3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 t rc t ras t rp t ras t rcd t rcd t rcd t rrd t rrd ax0 ax1 ax2 ax3 ax4 ax5 ax6 ax7 by0 by1 by4 by5 by6 cz0 raa raa cax rbb rbb cby rac rac caz * ap is the internal precharge start timing active read active active read t cac t cac t cac clk dq cke dqm a10 we cas ras cs read ap* ap* bs1 bs0 t ras t rp
w9812g2gh publication release date:may 19, 2008 - 27 - revision a09 11.5 interleaved bank write (burst length = 8) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 t rc t ras t rp t ras t rp t rcd t rcd t rcd t rrd t rrd raa raa cax rbb rbb cby rac rac caz ax0 ax1 ax4 ax5 ax6 ax7 by0 by1 by2 by3 by4 by5 by6 by7 cz0 cz1 cz2 write precharge active active write precharge active write clk dq cke dqm a0-a9, a11 a10 bs0 we cas ras cs bs1 idle bank #0 bank #1 bank #2 bank #3 t ras
w9812g2gh publication release date:may 19, 2008 - 28 - revision a09 11.6 interleaved bank write (burst length = 8, auto-precharge) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 t rc t ras t rp t ras t rcd t rcd t rcd t rrd t rrd raa raa cax rbb rbb cby rab rac ax0 ax1 ax4 ax5 ax6 ax7 by0 by1 by2 by3 by4 by5 by6 by7 cz0 cz1 cz2 caz * ap is the internal precharge start timing clk dq cke dqm a0-a9 a11 a10 bs0 we cas ras cs bs1 active write write active bank #0 idle bank #1 bank #2 bank #3 ap* active write ap*
w9812g2gh publication release date:may 19, 2008 - 29 - revision a09 11.7 page mode read (burst length = 4, cas latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 t ccd t ccd t ccd t ras t rp t ras t rp t rcd t rcd t rrd raa raa cai rbb rbb cbx cay cam cbz a0 a1 a2 a3 bx0 bx1 ay0 ay1 ay2 am0 am1 am2 bz0 bz1 bz2 bz3 * ap is the internal precharge start timing clk dq cke dqm a0-a9, a11 a10 bs0 we cas ras cs bs1 active read active read read read read precharge t ac t ac t ac t ac t ac bank #0 idle bank #1 bank #2 bank #3 ap*
w9812g2gh publication release date:may 19, 2008 - 30 - revision a09 11.8 page mode read / write (burst length = 8, cas latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 t ras t rp t rcd t wr raa raa cax cay ax0 ax1 ax2 ax3 ax4 ax5 ay1 ay0 ay2 ay4 ay3 qq q q q q dd d d d clk dq cke dqm a0-a9, a11 a10 bs0 we cas ras cs bs1 active read write precharge t ac bank #0 idle bank #1 bank #2 bank #3
w9812g2gh publication release date:may 19, 2008 - 31 - revision a09 11.9 auto-precharge read (burst length = 4, cas latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 clk dq cke dqm a0-a9, a11 a10 bs1 we cas ras cs bs0 t rc t rc t ras t rp t ras t rp t rcd t rcd t ac active read ap* active read raa rab raa caw rab cax aw0 aw1 aw2 aw3 * ap is the internal precharge start timing bank #0 idle bank #1 bank #2 bank #3 t ac ap* bx0 bx1 bx2 bx3
w9812g2gh publication release date:may 19, 2008 - 32 - revision a09 11.10 auto-precharge write (burst length = 4) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 clk dq cke dqm a0-a9, a11 a10 bs1 we cas ras cs bs0 t rc t rc t ras t rp t ras t rp raa t rcd t rcd rab rac raa caw rab cax rac aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3 active active write ap* active write ap* * ap is the internal precharge start timing bank #0 idle bank #1 bank #2 bank #3
w9812g2gh publication release date:may 19, 2008 - 33 - revision a09 11.11 auto refresh cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 all banks prechage auto refresh auto refresh (arbitrary cycle) t rc t rp t rc clk dq cke dqm a0-a9, a11 a10 we cas ras cs bs0,1
w9812g2gh publication release date:may 19, 2008 - 34 - revision a09 11.12 self refresh cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 (clk = 100 mhz) clk dq cke dqm a0-a9, a11 a10 bs0,1 we cas ras cs t cks t sb t cks t cks all banks precharge self refresh entry arbitrary cycle t rp self refresh cycle t xsr no operation / command inhibit self refresh exit
w9812g2gh publication release date:may 19, 2008 - 35 - revision a09 11.13 burst read and single write (burst length = 4, cas latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 clk cs ras cas we bs0 bs1 a10 a0-a9, a11 dqm cke dq t rcd rba rba cbv cbw cbx cby cbz av0 av1 av2 av3 aw0 ax0 ay0 az0 az1 az2 az3 qq q q d d d qqqq t ac t ac read read single write active bank #0 idle bank #1 bank #2 bank #3
w9812g2gh publication release date:may 19, 2008 - 36 - revision a09 11.14 power down mode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 raa caa raa cax raa raa ax0 ax1 ax2 ax3 t sb t cks t cks t cks t sb t cks active standby power down mode precharge standby power down mode active nop precharge nop active note: the powerdown mode is entered by asserting cke "low". all input/output buffers (except cke buffers) are turned off in the power down mode. when cke goes high, command input must be no operation at next clk rising edge. violating refresh requirements during power-down may result in a loss of data. clk dq cke dqm a0-a9 a11 a10 bs we cas ras cs read
w9812g2gh publication release date:may 19, 2008 - 37 - revision a09 11.15 auto-precharge timing (read cycle) read ap 0 11 10 9 8 7 6 5 4 3 2 1 q0 q0 read ap act q1 read ap act q1 q2 ap act read act q0 q3 (1) cas latency=2 read act ap when the auto precharge command is asserted, the period from bank activate command to the start of internal precgarging must be at least t ras (min). represents the read with auto precharge command. represents the start of internal precharging. represents the bank activate command. note: t rp t rp t rp ( a ) burst length = 1 command ( b ) burst length = 2 command ( c ) burst length = 4 command ( d ) burst length = 8 command dq dq dq dq q0 q1 q2 q3 q4 q5 q6 q7 t rp q0 read ap act q0 read ap act q1 q0 read ap act q1 q2 q3 read ap act q0 q1 q2 q3 q4 q5 q6 q7 (2) cas latency=3 t rp t rp t rp t rp ( a ) burst length = 1 command ( b ) burst length = 2 command ( c ) burst length = 4 command ( d ) burst length = 8 command dq dq dq dq
w9812g2gh publication release date:may 19, 2008 - 38 - revision a09 11.16 auto-precharge timing (write cycle) act 01 3 2 (1) cas latency = 2 (a) burst length = 1 dq 45 7 6891 1 10 write d0 act ap command (b) burst length = 2 dq write d0 act ap command trp trp d1 (c) burst length = 4 dq write d0 act ap command trp d1 (d) burst length = 8 dq write d0 act ap command trp d1 d2 d3 d2 d3 d4 d5 d6 d7 (2) cas latency = 3 (a) burst length = 1 dq write d0 act ap command (b) burst length = 2 dq write d0 act ap command trp trp d1 (c) burst length = 4 dq write d0 act ap command trp d1 (d) burst length = 8 dq write d0 ap command trp d1 d2 d3 d2 d3 d4 d5 d6 d7 twr twr twr twr twr twr twr twr 12 act represents the write with auto precharge command. represents the start of internal precharing. represents the bank active command. write ap act act when the /auto precharge command is asserted,the period from bank activate command to the start of intermal precgarging must be at least tras (min). note ) clk
w9812g2gh publication release date:may 19, 2008 - 39 - revision a09 11.17 timing chart of read to write cycle note: the output data must be masked by dqm to avoid i/o conflict 11 10 9 8 7 6 5 4 3 2 1 0 (1) cas latency=2 in the case of burst length = 4 read read write write dq dq ( b ) command dqm dqm d0 d1 d2 d3 d0 d1 d2 d3 ( a ) command (2) cas latency=3 read write read write d0 d1 d2 d3 ( a ) command dq dq dqm ( b ) command dqm d0 d1 d2 d3 11.18 timing chart of write to read cycle read write 0 11 10 9 8 7 6 5 4 3 2 1 q0 read q1 q2 q3 read read write write q0 q1 q2 q3 write q0 q1 q2 q3 d0 d1 dq dq ( a ) command dq dq dqm ( b ) command dqm ( a ) command ( b ) command dqm dqm in the case of burst length=4 (1) cas latency=2 (2) cas latency=3 d0 d0 d1 q0 q1 q2 q3 d0
w9812g2gh publication release date:may 19, 2008 - 40 - revision a09 11.19 timing chart of burst stop cycle (burst stop command) read bst 0 11 10 9 8 7 6 5 4 3 2 1 dq q0 q1 q2 q3 bst ( a ) cas latency =2 command ( b )cas latency = 3 (1) read cycle q4 (2) write cycle command read command q0 q1 q2 q3 q4 q0 q1 q2 q3 q4 dq dq write bst note: represents the burst stop command bst 11.20 timing chart of burst st op cycle (precharge command) 01 11 1098765432 (1) read cycle (a) cas latency =2 command q0 q1 q2 q3 q4 prcg read (b) cas latency =3 command q0 q1 q2 q3 q4 prcg read dq dq (2) write cycle (a) cas latency =2 command q0 q1 q2 q3 q4 prcg write (b) cas latency =3 command q0 q1 q2 q3 q4 write dq dq dqm dqm prcg twr twr
w9812g2gh publication release date:may 19, 2008 - 41 - revision a09 11.21 cke/dqm input timing (write cycle) 7 6 5 4 3 2 1 cke mask ( 1 ) d1 d6 d5 d3 d2 clk cycle no. external internal cke dqm dq 7 6 5 4 3 2 1 ( 2 ) d1 d6 d5 d3 d2 clk cycle no. external internal cke dqm dq 7 6 5 4 3 2 1 ( 3 ) d1 d6 d5 d4 d3 d2 clk cycle no. external cke dqm dq dqm mask dqm mask cke mask cke mask internal clk clk clk
w9812g2gh publication release date:may 19, 2008 - 42 - revision a09 11.22 cke/dqm input timing (read cycle) 7 6 5 4 3 2 1 ( 1 ) q1 q6 q4 q3 q2 clk cycle no. external internal cke dqm dq open open 7 6 5 4 3 2 1 q1 q6 q3 q2 clk cycle no. external internal cke dqm dq open ( 2 ) 7 6 5 4 3 2 1 q1 q6 q2 clk cycle no. external internal cke dqm dq q5 q4 ( 3 ) q4 clk clk clk q3
w9812g2gh publication release date:may 19, 2008 - 43 - revision a09 12. package specification 12.1 86l tsop (ii)-400 mil seating plane e d a2 a1 a b zd 1 43 86 44 e h e y l c l1 q zd 0.61 0.024 0.002 0.007 max. min. nom. a2 b a a1 0.17 1.00 0.05 0.27 1.20 0.15 sym. dimension (mm) max. min. nom. e 0.50 0.020 0.016 l 0.40 0.50 0.60 0.020 0.024 0.396 e 10.06 10.16 10.26 0.400 0.404 0.871 d 22.22 22.12 22.62 0.875 0.905 0.039 0.011 0.047 0.006 dimension (inch) l1 0.80 0.032 c 0.12 0.005 0.455 11.76 11.56 11.96 0.463 0.471 h e y 0.10 0.004 controlling dimension: millimeters 0.21 0.008
w9812g2gh publication release date:may 19, 2008 - 44 - revision a09 13. revision history version date page description a01 mar. 24, 2006 all create new document a02 sep. 08, 2006 10 exit auto refres h to next command is specified by t rc a03 sep. 27, 2006 18 modify characteristics notes 8 and add notes 9 (t t ) a04 oct. 03, 2006 16 add t xsr timing specification a05 nov. 10, 2006 3,14, 15,16,17 add -6c grade a06 jun. 06, 2007 3,14,15,16 add -6i grade a07 aug. 13, 2007 16 revise transient time t t ac test condition and calculate formula for compensation consideration in notes 6, 8 of ac characteristics and operating condition a08 feb. 14, 2008 3,14,15,16,17 add -6f grade and remove ac testing conditions table in notes 6 3,14,15,16 add -5 grade and remove -6f grade a09 may 19, 2008 3,14,15,16,17 change power supply voltage -6c grade from 3.0v~3.6v to 2.7v~3.6v important notice winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surg ical implantation, at omic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. further more, winbond products are not intended for applications wherein failure of winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify winbond for any damages resulting from such improper use or sales.

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